giu 13, 2023

The four grades of semiconductor packages, their role and evolution

When mailing fragile items, it is especially important to use the right packaging material, as it ensures that the package will reach its destination intact. Styrofoam, bubble wrap and sturdy boxes can all be effective in protecting the contents of a package. Similarly, packaging is a key part of the semiconductor manufacturing process, protecting chips from physical or chemical damage. However, the role of semiconductor packaging does not stop there.

In this article, the second in a series on semiconductor back-end processes, we will detail the different levels, roles and evolution of packaging technology.

The four levels of semiconductor packaging processes

Electronic packaging technology is related to the hardware structure of the device. These hardware structures include active components1 (e.g. semiconductors) and passive components2 (e.g. resistors and capacitors3). Therefore, electronic packaging technology covers a wide range and can be classified into four different levels such as level 0 packaging to level 3 packaging. Figure 1 illustrates the entire flow of the semiconductor packaging process. First is Level 0 packaging, which is responsible for cutting out the wafers; second is Level 1 packaging, which is essentially chip-level packaging; next is Level 2 packaging, which is responsible for mounting the chip onto a module or circuit card; and finally is Level 3 packaging, which mounts the circuit card with the chip and module attached to the system board. In a broad sense, the entire process is often referred to as "packaging" or "assembly". However, in the semiconductor industry, semiconductor packaging generally involves only the wafer dicing and chip-level packaging processes.

1 Active component: A device that requires an external power source to perform its specific function, like a semiconductor memory or a logic semiconductor.

2 Passive component: a device that does not have active functions such as amplification or conversion of electrical energy.

3 Capacitor (Capacitor): a component that stores charge and provides electrical capacity.

Packages are typically in the form of fine-pitch ball grid arrays (FBGA) or thin small form factor packages (TSOP), as shown in Figure 2. The tin 4-ball in the FBGA package and the lead 5 in the TSOP package act as pins, respectively, enabling electrical and mechanical connections between the packaged chip and external components.

4Tin (Solder): A low melting point metal that supports electrical and mechanical bonding.

5 Lead (Lead): A wire leading outward from a circuit or component terminal for connection to a circuit board.

▲Figure 3: Role of semiconductor packages (Source: ⓒ HANOL Press)

In addition, the semiconductor package enables electrical and mechanical connections from the chip to the system. The package supplies power to the chip through the electrical connection between the chip and the system, and provides the input and output paths of signals to the chip. In terms of mechanical connection, the chip needs to be reliably connected to the system to ensure a good connection between the chip and the system during use.

At the same time, the package needs to quickly dissipate the heat generated by the semiconductor chip and device. During the operation of a semiconductor product, heat is generated when current passes through a resistor. As shown in Figure 3, the semiconductor package completely encloses the chip. If the semiconductor package does not dissipate heat effectively, the chip may overheat, causing the internal transistors to heat up too quickly and become inoperable. Therefore, for semiconductor packaging technology, effective heat dissipation is critical. As semiconductor products become faster and more functional, the cooling function of the package becomes more and more important.

Trends in semiconductor packaging

Figure 4 outlines the six major trends in semiconductor packaging technology in recent years. Analyzing these trends helps us understand how packaging technology continues to evolve and play a role.

First, as heat dissipation has become an important factor in the packaging process, materials with better heat transfer6 performance and package structures that can effectively dissipate heat have been developed.

6 Heat conduction: refers to the process of transferring heat from a higher temperature part to an adjacent lower temperature part without involving material transfer.

Packaging technology that can support high-speed electrical signal transmission has also become an important development trend, because packaging can limit the speed of semiconductor products. For example, when connecting a semiconductor chip or device with a speed of 20 gigabits per second (Gbps) to a semiconductor package device that supports only 2 gigabits per second (Gbps), the system perceives the semiconductor speed as 2 gigabits per second (Gbps). Since the electrical path to the system is created in the package, the speed of the semiconductor product is greatly affected by the package, regardless of the speed of the chip. This means that along with increasing chip speed, semiconductor packaging technology needs to be upgraded to increase transmission speed. This applies in particular to artificial intelligence technology and 5G wireless communication technology. In view of this, packaging technologies such as flip chip packaging7 and silicon through-hole (TSV)8 have emerged to support high-speed electrical signal transmission.

7 Flip Chip: An interconnection technology that connects a chip to a substrate by mounting the bump face down on the substrate.

8 Silicon through-hole (TSV): A vertical interconnect channel that passes completely through the silicon die or wafer to achieve silicon stacking.

▲Figure 4: Trends in semiconductor packaging technology (Source: ⓒ HANOL Press)

Another development trend is three-dimensional semiconductor stacking technology, which has contributed to the transformative development in the field of semiconductor packaging. In the past, a package housing contained only one chip, while today multiple chips can be stacked in a package housing using technologies such as multi-chip packaging (MCP) and system-level packaging (SiP)9.

9 System-in-Package (SiP): a packaging technology that integrates multiple devices into a single package body to form a system.

Packaging technology also shows the trend of miniaturization of semiconductor devices, i.e., reducing the size of products. As semiconductor products are increasingly used in mobile and even wearable products, miniaturization has become an important demand for customers. To meet this demand, many technologies have been created to reduce the size of packages.

In addition, semiconductor products are increasingly being used in a variety of environments. In addition to everyday environments such as gyms, offices or homes, semiconductors can be found in tropical rainforests, polar regions, deep oceans and even space. Since the basic role of packaging is to protect semiconductor chips and devices, highly reliable packaging technologies need to be developed to ensure that semiconductor products work properly even in such extreme environments.

Finally, since the semiconductor package is the final product, the packaging technology must not only achieve the desired function but also have a low manufacturing cost.

In addition to the above-mentioned trends aimed at advancing the specific role of packaging technology, another driver of the evolution of packaging technology is the development of the semiconductor industry as a whole. In Figure 5, the red line indicates the change in feature size of the printed circuit board (PCB)10 installed in the assembly process since the 1970s, and the green line indicates the change in feature size of CMOS transistors on wafers. Reducing the feature size helps to draw smaller patterns on printed circuit boards and wafers.

10 printed circuit boards (PCBs): semiconductor boards consisting of circuitry, and components soldered to the surface of the board. These boards are commonly used in electronic devices.

▲Figure 5: Changes in feature sizes of wafers and printed circuit boards over time (Source: ⓒ HANOL Press)

In the 1970s, the difference in feature size between printed circuit boards and wafers was relatively small. Today, wafers are moving into mass production while CMOS transistors with feature sizes smaller than 10 nanometers (nm) are being developed, while the feature sizes of printed circuit boards are still in the 100 micron (um) range. The gap between the two feature sizes has widened significantly in the last few decades.

As motherboards are manufactured in panel form and subject to cost-saving strategies, among other factors, the feature size of printed circuit boards has not changed much. However, with advances in photolithography, the feature size of CMOS transistors has shrunk significantly, which has gradually widened the gap between the size of CMOS transistors and that of printed circuit boards. The problem, however, is that semiconductor packaging technology needs to personalize the chips cut from wafers and mount them on printed circuit boards, so it is necessary to bridge the size gap between printed circuit boards and wafers. In the past, the difference in feature size between the two was not significant, and thus through-hole technologies such as double in-line package (DIP)11 or sawtooth single in-line package (ZIP)12 could be used to insert semiconductor package leads into printed circuit board sockets. However, as the difference in feature size between the two grew, it became necessary to use surface mount technologies (SMT)13 such as thin small form factor packages (TSOPs) to secure the leads to the surface of the motherboard. Subsequently, packaging technologies such as ball grid array (BGA), flip-chip package, fan-out wafer-level chip size package (WLCSP)14 and silicon through-hole (TSV) were introduced to bridge the expanding size difference between the wafer and the motherboard.

11 Dual In-Line Package (DIP): a package technology where the electrical connection pins are arranged in two rows.

12 Saw-tooth single-in-line package (ZIP): a package technology where the pins are arranged in a saw-tooth pattern, an alternative technology to the two-row inline package, which can be used to increase mounting density.

13 Surface Mount Technology (SMT): A packaging method that mounts the chip to the surface of the system board by soldering.

14 Wafer Level Chip Size Packaging (WLCSP): A technology for packaging integrated circuits at the wafer level, a variation of the flip-chip packaging technology. Fan-out wafer-level chip-size packaging (WLCSP) is characterized by connections that extend beyond ("fan-out") the surface of the chip.

Ensuring the validity of semiconductor packages through testing

There are two ways to develop a semiconductor package and ensure its validity. The first approach is to use existing packaging technology to create a package suitable for a newly developed semiconductor chip, and then evaluate the package. The second approach is to develop a new semiconductor package technology, apply it to an existing chip, and evaluate the effectiveness of the new package technology.

In general, the development of a new chip and the application of a new packaging technology do not occur simultaneously. The reason is that if both the chip and the package are not tested, it is difficult to determine the cause of the problem once it occurs after the package is completed. In view of this, the industry will use existing mass-produced chips with fewer known defects to test the new packaging technology in order to verify the packaging technology separately. Only after the packaging technology has been validated will it be applied to the development of new chips, and then to the production of semiconductor products.

Figure 6 illustrates the packaging technology development process for a new chip. Usually, when manufacturing semiconductor products, chip design and package design development are done simultaneously to optimize their characteristics as a whole. In view of this, the packaging department will first consider whether the chip is packageable before the chip design. During the feasibility study, the package design is first roughly tested to analyze the electrical evaluation, thermal evaluation and structural evaluation in order to avoid problems in the actual mass production phase. In this case, the semiconductor package design is the wiring design of the substrate or leadframe, as this is the medium for mounting the chip to the motherboard.

The packaging department provides feedback to the chip designer on the feasibility of the package based on the interim design and analysis of the package. Only when the package feasibility study is completed is the chip design considered complete. Next comes wafer fabrication. During the wafer fabrication process, the packaging department will simultaneously design the substrate or leadframe required for package production, and the back-end manufacturing company will continue to complete the production. At the same time, the package process is prepared in advance and package production starts as soon as the wafer testing is completed and delivered to the package department.

▲ Figure 6: Development process of semiconductor packaging technology (Source: ⓒ HANOL Press)

Semiconductor products must be packaged to test and verify their physical characteristics. At the same time, the design and process can be examined by evaluation methods such as reliability testing. If the characteristics and reliability are not satisfactory, the cause needs to be determined and the packaging process is repeated again after the problem is solved. Ultimately, package development is not complete until the desired characteristics and reliability criteria are met.

Perspectives on the role of semiconductor packaging

In examining the role of packaging technology in protecting and connecting the various components of a semiconductor, it is also critical to understand the materials and methods used in the packaging process. The next article will explore the differences between conventional and wafer-level packaging, and how different packaging methods affect the quality and efficiency of the packaging process.

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